The split-gate non-volatile memory is a configuration that has been widely used in medium-low density applications. As shown in FIG. 1A, a version of the split-gate non-volatile memory includes source/drain regions 101 in a substrate 103, dielectric spacers 105, a word gate 107 over a gate oxide 109, and a control gate (CG) 111 on an interpoly dielectric (IPD) layer 113 over a floating gate (FG) 115 and a tunneling oxide (TO) layer 117. Another version of the split-gate technology is a split-gate charge trapping (CT) non-volatile memory illustrated in FIG. 1B. Rather than the TO/FG/IPD combination in the version of FIG. 1A, the split-gate CT non-volatile memory includes a tunneling oxide (TO) layer 119, a charge trapping (CT) layer 121, and a blocking oxide (BO) layer 123. One example of such a device is Silicon-Oxide-Nitride-Oxide-Silicon (SONOS). These memory devices may be programmed by mechanisms such as source side injection (SSI) or channel hot electron (CHE). Fowler-Nordheim (FN) tunneling or band-to-band tunneling hot holes (BBHH) may be utilized to remove charges.
Efforts have been made to increase the program/erase speed for scaled power supply voltage, minimize program disturbance as by enhancing punchthrough immunity, improve endurance of the structures, and efficiently remove trapped charges at the sidewall charge trapping layer to prevent their adverse effects and reduce performance fluctuations. For example, adverting to FIG. 2A, in addition to source/drain regions 201 and implant regions 203 in the substrate 205, dielectric spacers 207, a word gate 209, and a control gate 211, the structure includes an epitaxial layer 213 with light doping for low control gate voltage and a recessed word gate channel for higher injection efficiency.
The approach illustrated in FIG. 2A has proven problematic in several respects. For example, as illustrated in FIG. 2B, the cell size is limited by the source/drain punchthrough immunity during program disturbance. As the source and drain junctions are deep and at the same level, it is more susceptible to punchthrough 215, especially if the channel under the word gate is a narrow bandgap material. Moreover, trapped charges 217 at the sidewall are difficult to remove and interfere with program/erase speed, resulting in cell performance fluctuations.
A need therefore exists for split-gate flash memory devices with improved program and erase performance, reduced punchthrough, and enabling methodology.